1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method of manufacturing a semiconductor device having a build-up layer for wiring between semiconductor elements and external connection terminals.
2. Description of the Related Art
In recent years, LSI technologies as a key technology for multimedia devices have been steadily advanced to improve data transmission speed and capacity. With the advancement of the LSI technologies, high-density mounting techniques for interfaces between LSIs and electronic devices have also been developed. Among semiconductor packages, CSPs (Chip Size Package), whose size is substantially equal to the chip size, can offer high-density mountability.
Although there are a variety of types of CSPs, most of the CSPs are configured to have an interposer between semiconductor elements and connection terminals (e.g. solder bumps) for external connection. This is because pads on semiconductor elements are highly accurately formed by a wafer process whereas external connection terminals only need to be accurate enough to satisfy pitch based on wiring rules and therefore do not have accuracy as high as the accuracy of the pads. Therefore, an interposer is provided between the semiconductor elements and the external connection terminals.
Resin substrates have been used as interposers, and a wire bonding method or a flip-chip bonding method has been employed for connecting semiconductor elements to an interposer. However, as density of semiconductor elements grows and their size decreases, it is becoming difficult to form electrodes on a resin substrate to correspond to pads of semiconductor elements due to an accuracy difference between the semiconductor elements and the resin substrate. As a result, resin substrates are becoming less appropriate as interposers for CSPs.
In view of these circumstances, Japanese Patent Laid-Open Publication No. 2002-16173 discloses a semiconductor device manufacturing method wherein an interposer for a CSP is formed by a build-up method. According to this semiconductor device manufacturing method, a wafer is divided into semiconductor elements by a dicing process. Each of the semiconductor elements is mounted on a recessed part formed on a substrate. Then, an insulating layer having an inter-layer conductive part is formed thereon. Further, a build-up layer electrically connected to the inter-layer conductive part is formed by a build-up process.
However, in the case where a build-up process is performed after dividing a wafer into semiconductor elements and mounting the semiconductor elements on the substrate as described above, the semiconductor elements need to be accurately positioned on the substrate if the semiconductor elements have high density and high accuracy. Therefore, positioning of the semiconductor elements becomes difficult. Besides, when the semiconductor elements are separated before the build-up process, handling of the separated semiconductor elements is troublesome.
A solution for these problems may be semiconductor device manufacturing methods based on a wafer level process that are designed to form a build-up layer at a wafer level, i.e., before dividing semiconductor elements provided on a wafer. According to the methods based on the wafer level process, however, the area of a build-up layer has the same size as the area of semiconductor elements separated by the dicing, and cannot be formed wider than that. This results in low flexibility of wiring arrangement of the build-up layer.